1. Field of the Invention
The invention relates to a circuit for recording digital waveform data and a method of recording digital waveform data, and more particularly to such a circuit and a method both of which are capable of reducing capacity of a memory in which data is to be stored.
2. Description of the Related Art
A circuit for recording digital waveform data is used for storing signal waveforms in a large-scale integrated circuit (LSI). Such a circuit is generally arranged outside the LSI, and is electrically connected to the LSI through it's signal pins.
In these days, with higher integration in LSIs, the LSI has been fabricated as a system-on-chip (SOC) having a plurality of LSIs integrated into a single LSI. In the SOC, it is quite difficult to externally output signals necessary for monitoring the operation of a target LSI.
As one of the solutions to such a problem, those skilled in the art could readily suggest that a circuit for recording digital waveform data be mounted on an LSI to be monitored. However, if a circuit for recording digital waveform data was large in size, the cost for fabricating the LSI would increase. Hence, there has been a need for a small-sized circuit for recording digital waveform data.
FIG. 1 shows an example of operation in a conventional method of recording digital waveform data. For instance, when data, shown in FIG. 2, is stored in a circuit for recording digital waveform data, the data is stored in a memory in the order shown without any processing.
The conventional method illustrated in FIG. 1 requires a memory to have a capacity equal to the amount of input data, since input digital data is stored in the memory as it is. When a circuit for recording digital waveform data was arranged independently of and outside the LSI, the conventional method was frequently selected, because several memories could be used.
FIG. 3 shows another example of a conventional method of recording digital waveform data. In the illustrated method, when the same data is repeatedly input into a circuit, the amount of data stored in memory is reduced by storing the number of times the data repeats.
FIG. 3 shows a memory that stores the data illustrated in FIG. 2. The memory is designed to have a 1-bit storage area for each address. Such a 1-bit storage area is called a TAG bit. When the TAG bit is 0, data stored in an address associated with the TAG bit is new input data. In contrast, when the TAG bit is 1, data stored in an address associated with the TAG bit is the number of times the data stored in the previous address is repeated.
With reference to FIG. 3, since the data from D0 to D3 is associated with a TAG bit that is equal to 0, data from D0 to D3 are stored in a memory as they are. Data M is associated with a TAG bit that is equal to 1. Accordingly, data M indicates that the data stored in the previous address M times. (see FIG. 2).
In accordance with above-mentioned method, it would be possible to reduce the size of a memory that stores input data.
As a method of compressing data, “Computer. Encyclopedia” published by Asakura Shoten, Apr. 15, 1987, pp. 545, FIG. 4, suggests that if certain data is not used as ordinary data, the certain data is used for indicating the number of times the same data is repeated.
However, in order to use the above-mentioned method, data input into memory has to be fixed to a certain degree. Accordingly, the above-mentioned method is not applicable to a circuit for recording digital waveform data. In order to allow any data to be input into memory, the memory would have to include the TAG bits illustrated in FIG. 3.
The conventional method, illustrated in FIG. 3, that uses a TAG bit requires a smaller memory capacity than the conventional method illustrated in FIG. 1 where input data is stored as is. However, the conventional method illustrated in FIG. 3 requires a memory for storing TAG bits as well as a memory for storing digital waveform data, resulting in additional memory capacity for storing TAG bits.
Japanese Unexamined Patent Publication No. 8-255072 (A) has suggested an apparatus for transferring data that includes a data compressor. The data compressor compresses the data file, and the compressed data file is transmitted. The data compressor compresses a plurality of data blocks having the same content that are successively arranged in the data file, into a single data block having a block address of the first data block.
Japanese Unexamined Patent Publication No. 11-102310 (A) has suggested a program tracer that records address data of a program being executed. When a command sequence of the program carries out a loop process, the program tracer counts and records the number of loops in the loop process, and records only the address data regarding the command sequence of the final loop.
Japanese Unexamined Patent Publication No. 11-249869 (A) has suggested a computing apparatus that includes: a flexible operation network comprised of a plurality of computing units, a data-compressing circuit that compresses data to be computed when the same outputs are successively repeatedly transmitted from the operation network, a memory that stores both the data to be computed and the number of times the same outputs are repeated, and a data-expanding circuit for expanding the compressed data to data in an original form when the data is to be transmitted from the memory.
Japanese Unexamined Patent Publication No. 2001-30552 (A) has suggested a method of compressing received data in accordance with a pack-pit process, and transferring the thus compressed data, including the steps of: storing received data into a buffer, reading data out of the buffer and making a tag, overriding the tag in an area other than the area that different data is successively arranged, reading the tag out of the buffer, and transferring data stored in the buffer in accordance with a pack-pit process dependent on the tag.
However, the above-mentioned problem remains unsolved even in these Publications.